Publications | Dr. Ahmad Tarraf

2025

EquilibrIO: Taming the I/O Tides in High-Performance Computing

T. Özden, A. Tarraf, and F. Wolf
In Proc. of the 2025 IEEE International Conference on Cluster Computing (CLUSTER), Edinburgh, Scotland, UK, Sep. 2025 (accepted)

Dynamic Resources Management for Exascale in ADMIRE Framework

J. Carretero, David E. Singh, J. Fernandez-Muñoz, R. Sedona, S. Pernice, B. Cantalupo, M. Aldinucci, M. Torquati, A. Tarraf, E. Jeannot, and F. Wolf
Procedia Computer Science (accepted)

Accelerating Sheet Metal Forming with AI

E. Park, C. Woll, K. Kassem-Mathey, K. Diethelm, S. Burka, C. Terboven, A. Tarraf, and F. Wolf
In Proc. of the NAFEMS DACH Conference 2025, Salzburg, Austria, pages 1–12, May 2025
https://www.nafems.org/publications/resource_center/nwc25-0007434-paper/

A Deep Look Into the Temporal I/O Behavior of HPC Applications -- Extended Version

F. Boito, L. Teylo, M. Popov, T. Jolivel, F. Tessier, J. Luettgau, J. Monniot, A. Tarraf, A. R. Carneiro, and C. Osthoff
https://inria.hal.science/hal-04978752

A Deep Look Into the Temporal I/O Behavior of HPC Applications

F. Boito, L. Teylo, M. Popov, T. Jolivel, F. Tessier, J. Luettgau, J. Monniot, A. Tarraf, A. R. Carneiro, and C. Osthoff
In Proc. of the 2025 IEEE International Parallel and Distributed Processing Symposium (IPDPS), Milano, Italy, June 2025
https://inria.hal.science/hal-04887809

A Simulation-Based Framework to Reduce I/O Contention in HPC

S. Pernice, A. Tarraf, J.-B. Besnard, B. Cantalupo, D. E. Singh, A. C. Garcia, F. Wolf, S. Shende, J. Carretero, and M. Aldinucci
In Proc. of the 2025 IEEE International Parallel and Distributed Processing Symposium (IPDPS), Milano, Italy, June 2025, pp. 1–2

2024

I/O Behind the Scenes: Bandwidth Requirements of HPC Applications With Asynchronous I/O

A. Tarraf, J. Fernandez-Muñoz, D. E. Singh, T. Özden, J. Carretero, and F. Wolf
In Proc. of the 2024 IEEE International Conference on Cluster Computing (CLUSTER), Kobe, Japan, Sep. 2024
https://ieeexplore.ieee.org/document/10740891

Malleability in modern HPC systems: Current experiences, challenges, and future opportunities

A. Tarraf, M. Schreiber, A. Cascajo, J. B. Besnard, M. Vef, D. Huber, H. Sonja, A. Brinkmann, D. E. Singh, H. C. Hoppe, A. Miranda, A. J. Peña, R. Machado, M. García-Gasulla, M. Schulz, P. Carpenter, S. Pickartz, T. Rotaru, S. Iserte, V. Lopez, J. Ejarque, H. Sirwani, C. D. Carothers, J. Carretero, F. Wolf
IEEE Transactions on Parallel and Distributed Systems, vol. 35, no. 6, pp. 1–14, Jun. 2024
doi: 10.1109/TPDS.2024.3406764
https://ieeexplore.ieee.org/document/10541114

Capturing Periodic I/O Using Frequency Techniques

A. Tarraf, A. Bandet, F. Boito, G. Pallez, and F. Wolf
In Proc. of the 38th IEEE International Parallel and Distributed Processing Symposium (IPDPS), San Francisco, CA, USA, pages 1–14, IEEE, May 2024.
https://ieeexplore.ieee.org/document/10579160

Introducing the metric proxy for holistic I/O measurements

J.-B. Besnard, A. Tarraf, A. Cascajo, and S. Shende
In Proc. of the 10th HPC I/O in the data center workshop (HPC-IODC’24), held in conjunction with the ISC high performance conference, Hamburg, Germany, May 2024
https://link.springer.com/chapter/10.1007/978-3-031-73716-9_15

2023

Towards Smarter Schedulers: Molding Jobs into the Right Shape via Monitoring and Modeling

J.-B. Besnard, A. Tarraf, C. Barthélemy, A. Cascajo, E. Jeannot, S. Shende, and F. Wolf
In Proc. of the 2nd International Workshop on Malleability Techniques Applications in High-Performance Computing (HPCMALL 2023), held in conjunction with the ISC High Performance Conference (ISC), Hamburg, Germany, volume 13999, pages 68–81, Springer, May 2023
https://doi.org/10.1007/978-3-031-40843-4_6

2022

Conquering Noise With Hardware Counters on HPC Systems

M. Ritter, A. Tarraf, A. Geiß, N. Daoud, B. Mohr, and F. Wolf
In Proc. of the Workshop on Programming and Performance Visualization Tools (ProTools), held in conjunction with the Supercomputing Conference (SC22), pages 1-10, IEEE, 2022
https://ieeexplore.ieee.org/document/10027495

2021

2020

From Transistor Level to Cyber Physical/Hybrid Systems: Formal Verification Using Automatic Compositional Abstraction

A. Tarraf and L. Hedrich
IT - Information Technology, 2020
https://doi.org/10.1515/itit-2020-0004

Modeling Circuits with Parameter Variation by ELSA: Eigenvalue Based Linear Hybrid System Abstraction

A. Tarraf and L. Hedrich
17. GMM/ITG-Fachtagung ANALOG, 2020
https://ieeexplore.ieee.org/document/9257336

Equivalence Checking Methods for Analog Circuits Using Continuous Reachable Sets

A. Tarraf, N. Kochdumper, M. Rechmal, L. Hedrich, and M. Olbrich
In Proc. of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Limassol, Cyprus, 2020
https://ieeexplore.ieee.org/abstract/document/9154965

Verification of modeling: metrics and methodologies

A. Tarraf and L. Hedrich
Modelling methodologies in analog integrated circuit design*, G. Dündar and M. B. Yelten (Eds.), Institution of Engineering & Technology, 2020, pp. 95–116
https://shop.theiet.org/modelling-methodologies-in-analogue-integrated-circuit-design

Establishing Reachset Conformance for the Formal Analysis of Analog Circuits

N. Kochdumper, A. Tarraf, M. Rechmal, M. Olbrich, L. Hedrich, and M. Althoff
In Proc. of the 25th Asia and South Pacific Design Automation Conference (ASP-DAC), Beijing, China, 2020,
https://ieeexplore.ieee.org/document/9045120

2019

Multi-agent learning for energy-aware placement of autonomous vehicles

Ö. Erduran, M. Minor, A. Tarraf, L. Hedrich, F. Rühl, H. Schroth
In Proc. of the 18th IEEE International Conference On Machine Learning And Applications (ICMLA), Boca Raton, FL, USA, 2019
https://ieeexplore.ieee.org/document/8999048

Automatic Modeling of Transistor Level Circuits by Hybrid Systems with Parameter Variable Matrices

A. Tarraf and L. Hedrich
In Proc. of the International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), Lausanne, Switzerland, July 2019
https://ieeexplore.ieee.org/document/8795271

Behavioral Modeling of Transistor-Level Circuits Using Automatic Abstraction to Hybrid Automata

A. Tarraf and L. Hedrich
In Proc. the Design, Automation & Test in Europe Conference & Exhibition (DATE), Florence, Italy, 2019
https://ieeexplore.ieee.org/document/8715184

2018

Automatic Abstraction of Analog Circuits to Hybrid Automata

A. Tarraf and L. Hedrich
16. GMM/ITG-Fachtagung Analog, Munich, Germany, 2018
https://ieeexplore.ieee.org/document/8576836

Automatic Abstraction of Transistor Level Circuits to Hybrid Automata

A. Tarraf and L. Hedrich
In Proc. of Frontiers in Analog CAD (FAC), Vienna, Austria, 2018
http://tool.em.cs.uni-frankfurt.de/~tarraf/Public/tarraf-fac18.pdf

2017

Flachheitsbasierte Trajektoriengenerierung und Folgeregelung mit modellprädiktiver und modellfreier Regelung

T. Raste and A. Tarraf
In Proc. of VDI/VDE Fachtagung AUTOREG, Berlin, 2017
https://www.vdi-nachrichten.com/wp-content/uploads/2019/09/9804_InhaltsverzeichnisWeb-2292.pdf